#intelArcDay2021 Chapter 3 - intel thread director and alderlake by Rajshree and Arik youtu.be/lm6vovVFo70
An exciting day! @Rajaontheedge unveils Intel’s next-gen client and data center architectures, Alder Lake and Sapphire Rapids, at Architecture Day – all built on Intel 7! scq.io/ot6Qdjg
Hello, hybrid: Intel is dishing details on its Alder Lake chip due in PCs later this year. It marries high-performance cores for speed with high-efficiency cores for battery life. Yes, that's just what Apple does with M1 and Qualcomm does with Snapdragon. cnet.co/3gicvF3
As the company has been teasing since last year’s Architecture Day, Alder Lake will feature Intel’s latest hybrid architecture: instead of simply offering the next generation of powerful Intel CPU cores, it’ll offer a mix of both performance and efficiency x86 cores, both of which Intel previewed as part of its announcements.
Additionally, Alder Lake will be the first chip released on Intel’s newly renamed Intel 7 technology node (not to be confused with Intel 4, which was previously known as Intel’s delayed 7nm node, and will be available to consumers sometime in 2023 under the codename “Meteor Lake”). Intel 7 still uses similar technology to the company’s current 10nm tech, instead of the bigger leap in manufacturing processes planned for Intel 4.
Meanwhile, the company’s new x86 Efficient core (codenamed “Gracemont”) aims to be “the world’s most efficient x86 CPU core” while still offering higher IPC than the company’s Skylake chips. Intel claims that for single-thread cases, one of its new efficient cores hits 40 percent more performance at the same power (or similar performance while using 40 percent of the power) of a Skylake core, improvements that double when comparing four Efficient cores running four threads to two Skylake cores running four threads.
Broadly speaking, the “performance” cores are the ones that have featured in Intel’s beefier Core-class processors, while the “efficiency” cores resemble the Atom-class processors in lower power devices. And each of those new architectures would be interesting on their own, but Intel plans to combine the two in a hybrid architecture as a core product to its lineup — starting with its upcoming Alder Lake chips this fall — that makes them far more notable.
The new Alder Lake chips, however, are aspiring to be far more ambitious. Intel teased a full range of chips from 9W to 125W that would utilize the new hybrid approach, combining multiple high-end performance cores with efficient cores for a wider range of power when users need it and efficiency when running less strenuous tasks.
Given that Intel’s announcements today largely focused on the architectures, there are no hard product announcements, but the company did tease several planned Alder Lake SoCs that would utilize the new cores. Those include a desktop SoC with eight performance cores, eight efficiency cores, and integrated memory, graphics, and I/O; a laptop SoC with six performance cores, eight efficiency cores, imaging, Thunderbolt 4 support, memory, I/O, and more powerful Xe graphics all integrated in; and an ultramobile-focused SoC with two performance cores and eight efficiency cores.
Intel, of course, isn’t the first company to use a combination of performance and efficiency cores for optimized computing; the concept has been a cornerstone of Arm’s big.LITTLE and DynamicIQ technologies for over a decade. It’s been a key part of the domination of Qualcomm’s Snapdragon chips for Android phones, Apple’s A-series chips in the iPhone, and — perhaps most relevant for comparison to Intel — Apple’s M1 computer chips (which feature four high-performance “Firestorm” and four energy-efficient “Icestorm” cores).
We’ll have to wait for the first Alder Lake chips to arrive in the coming months to see how Intel’s latest attempt at cracking hybrid computing holds up. But it’s clear from Architecture Day 2021 that Intel views it as not just a niche for in-between devices but as a key part of its product lineup going forward. Now all that’s left to do is see if it can deliver.
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Pick a core, any core, says Intel – we'll magically put the right workload onto one in a hybrid SoC or accelerator
19 August, 2021 - 08:13am
Intel has revealed some details about its upcoming chip designs, and claims they are the biggest and most significant change to its products for years.
This includes new CPUs and the Alder Lake family that places different types of core alongside each other in system-on-chip packages.
The chip giant is kinda taking a leaf out of the Arm world's book, here.
Arm-compatible smartphones, tablets, and PCs typically have a mix of CPU core types: some lightweight ones that are battery friendly and focused on running things like background tasks and less-demanding apps, and some that draw more power and are used only when applications need a surge in processing performance. The operating system should assign apps to the appropriate cores, ensuring software gets the right level of performance without draining the battery too much.
Intel is trying to go the same sort of route: one of its new CPU core types is called the Efficient Core – aka Gracemont – and Intel says that when compared to its 2015-era Skylake architecture, it "achieves 40 percent more performance at the same power or delivers the same performance while consuming less than 40 percent of the power."
As the name implies, Intel intends this E core to be used primarily in devices like thin and light laptops.
Some notable features: the E core has a 64KB L1 instruction cache, 32KB of L1 data cache, and up to 4MB of L2 cache shared by four cores. Spectre-be-damned, Intel is leaning hard into speculative execution to speed up software. This means improvements, we're told, to the branch prediction and prefetchers, and dual three-wide x86 instruction decoders – so up to six instructions per cycle queued up. The pipeline has a 256-entry out-of-order window, and 17 execution ports into the integer ALUs, numerous floating-point and vector math units, and memory access units.
The E core supports AVX vector math with extensions to accelerate integer-based machine-learning calculations.
Intel's overview of its Efficient Core ... Click to enlarge
And to complement the E core is the Intel Performance Core, previously discussed under the name Golden Cove. The P core includes Advanced Matrix Extensions, an acceleration engine designed to speed AI workloads. This core is also supposed to scale from laptops and desktop PCs to servers.
Like with the E, Intel says the P core uses all manner of new techniques and speculative execution to anticipate processing requirements and get stuff done efficiently. The P core has, among other things, six instruction decoders, a bigger and wider micro-op cache, 12 execution ports, bigger register files, improved branch prediction and prefetching, a 512-entry reorder buffer, faster math operations, 32KB of L1 instruction cache with a larger instruction TLB, 48KB of L1 data cache, and up to 2MB of L2 cache. More instructions are executed at the rename and allocation stage of the pipeline, too, interestingly.
And the P core ... Click to enlarge
All of which is lovely, we guess – but Intel's next-gen architectures typically improve this sort of thing. If you want the full details, Intel's presentations, slides, marketing, and so forth on its new architectures are here.
Crucially, this time around, Intel will put E cores and P cores in the same system-on-a-chip, and operating systems can decide which core and which type of core to use. This will be possible in forthcoming 10nm Alder Lake systems-on-a-chips that incorporate a mix of E and P cores, and new Intel tech called Thread Director.
Intel explained that Thread Director can detect a demanding workload like a game starting up and give it some P core time. If email is syncing in the background, it gets an E core. Thread Director can schedule to both types of cores and can detect idling workloads on a P core and shunt it off to an E core until it can justify use of the higher-performance part of the chip.
While talking this up as a new dawn of hybrid chips, Intel acknowledged that other chip designers have been here before, as we mentioned. Chipzilla's point of difference is a belief that its hybrids are all about performance, while rivals mix and match cores to control power consumption.
Windows 11 will be ready for Thread Director out of the box. Linux OS developers are aware it's coming. Whether Thread Director in Alder Lake matters to Linux and other OSes aimed at servers is moot as while Intel advances the P core as just the thing for "large code footprint applications," Alder Lake is a client-level architecture, meaning it's for PCs and laptops.
Happily, Intel is also using P cores in its new server silicon – code-named Sapphire Rapids – which will be marketed in the Xeon Scalable Processor name.
Sapphire Rapids puts Intel's "tiles" tech to work. Tiles are essentially individual processors, and Intel has figured out how to place multiple tiles in a single package that uses "embedded multi-die interconnect bridge" packaging to present all the tiles as a single, logical processor.
This rather reminds us of AMD's chiplets, in which multiple physical processor dies are included in one logical package. Our sister site The Next Platform has more on Intel's tile approach, here.
Tiles are how Intel plans to serve clouds and workloads like AI or microservices that require scale. Sapphire Rapids therefore represents a riposte to the many-core Arm-powered processors that the likes of Oracle and AWS are currently advancing as just the ticket for microservices in a one-core-one-container world.
The upcoming Sapphire Rapids Xeons are set to include the following features, all designed to speed servers.
The Accelerator Interfacing Architecture (AIA) might be the most significant because it's how Intel will offload housekeeping workloads, such as handling storage I/O or running virtual switches, into what it now prefers to call Infrastructure Processing Units (IPUs – aka DPUs.)
Intel execs at the 2.5-hour media briefing, dubbed Architecture Day, The Register attended earlier this week were cagey about exactly how AIA will put IPUs to work, mentioning collaboration with Microsoft and VMware. They were bullish at the prospect of reclaiming instruction cycles, pointing out that some microservices at Facebook spend between 31 and 83 per cent of server power on overheads. If that overhead work can be shifted to IPUs, the CPU cores will be free to do other things, we're told.
One possibility afforded by AIA was diskless servers: apparently an IPU, using the accelerator architecture, can provide a virtual NVMe device that uses external storage – even as a boot drive.
Intel suggested that IPUs and AIA will be big in clouds and among communications service providers, and that as-yet-unrevealed alliances will make IPUs relevant to even mainstream data center users.
And in a related non-surprise, Intel is now selling IPUs. The semiconductor giant revealed Mount Evans, its first dedicated IPU ASIC, and an FPGA-based IPU reference platform called Oak Springs Canyon.
The mere fact that Intel has prepared server processors ready for IPUs matters because hype about the devices and a new data center architecture they can enable has built for years, with little sign of how it will be realized. AIA shows IPUs/SmartNICs/DPUs are on their way to real use.
Another important accelerator in Sapphire Rapids is Advanced Matrix Extensions (AMX), silicon dedicated to tensor processing and therefore to deep-learning algorithms. AMX can work even as Sapphire Rapids P cores go about other business. AMX thus has its own instruction set.
The Next Platform has more analysis of AMX, here.
The other accelerator in Sapphire Rapids is the Data Streaming Accelerator (DSA) that takes care of moving data. This is another bottleneck-clearer aimed at ensuring data flows among the CPU cores, memory, caches, attached storage, and networked storage devices without leaving CPUs waiting for something to do.
If you need even more grunt, Intel has a bridge to sell you – the Ponte Vecchio GPU.
Ponte Vecchio is dripping with customizations for high-performance computing – whenever it arrives, it's supposed to be going into a top US supercomputer – but is as notable for its implementation of tiles and collaboration with TSMC.
The GPU features five tiles, each specializing in different chores and each made using different fabrication processes. The compute tile is built by Intel's Taiwanese rival TSMC, and Chipzilla is therefore keen to claim that Ponte Vecchio demonstrates its new IDM 2.0 strategy under which it just gets stuff done by working with whatever foundry is best-suited to the job, rather than only using stuff it built all by itself.
Intel also has new GPUs and a new brand for them – Arc – mostly aimed at gamers and content creators.
All of the above sounds like it'll be fun to play with.
Curb your enthusiasm, readers, because Intel can't quite say when much of it will land.
Ponte Vecchio is a sometime-in-2022 affair. Alder Lake will arrive "later this year" and it is unclear if PCs featuring it will arrive in time to let Windows 11 take advantage of Thread Director when the OS launches in "late 2021".
Intel CEO Pat Gelsinger only appeared at the end of the Architecture Day presentation and had little to say other than the new stuff representing a change in the way we need to think about chips. In the past, he said, new processes defined important advances in silicon technology. Packaging silicon into hybrid machines is where the action is today, he opined.
It didn't seem at all odd for Gelsinger to just put the cherry on top of all the technology announcements mentioned above, because he wasn't at the company when they were decided and developed.
Gelsinger is, however, in the big chair now that Intel must sell what it believes are market-making innovations, even as Arm presses deeper into Intel territory, Qualcomm advances its ambitions to run everywhere, AWS pushes its own silicon ahead of Xeons, AMD finds novel ways to attack, and Nvidia tries to muscle into almost every computing niche. ®
Facebook, a company perhaps not top of mind when it comes to enterprise applications, trust, or privacy, sees an opportunity to make the unloved video conferencing experience more convoluted, costly, and cartoonish.
On Thursday, the social ad giant's Oculus division, having recently recalled millions of itchy foam inserts in its Quest 2 VR headsets, introduced Horizon Workrooms, a virtual reality conferencing system. A suntanned Mark Zuckerberg even gave a interview to promote the concept of a Facebook metaverse.
The service is available as a free download to anyone who has a Quest 2 face-hugger and can recall where the device was last abandoned, or to anyone inspired to buy the headweight for $299, once post-recall sales resume next week.
More than ninety human rights groups from around the world have signed a letter condemning Apple's plans to scan devices for child sexual abuse material (CSAM) – and warned Cupertino could usher in "censorship, surveillance and persecution on a global basis."
The US-based Center for Democracy and Technology organised the open letter [PDF], which called on Apple to abandon its approach to mass-scanning. Signatories include Liberty and Big Brother Watch in the UK, the Tor Project, and Privacy International.
The letter raises concerns about the accuracy of Apple's technology, arguing that these kinds of algorithms are "prone to mistakenly flag art, health information, educational resources, advocacy messages, and other imagery." And then there are the consequences of governments getting involved.
Microsoft is set to be the only firm among the enterprise tech giants investing in robotic process automation (RPA) tools to make a significant impact, a report from Forrester claims.
The RPA market is set to be worth $2.9bn by revenue in 2021, up from $125m in 2016, while the two biggest players, Automation Anywhere and UiPath, have a combined $39.2bn.
It is tiny compared with the enterprise application market, worth $225bn in 2029, according to IDC, yet vendors in the bigger market are still tempted to get a slice of the action. Salesforce, SAP, Oracle, and Microsoft have all made significant investments knitting RPA into their platforms in recent years, but only the Redmond OS giant is likely to make headway, Forrester said.
Despite a record year in 2019 that many analysts believed would only be topped in 2020, a report by tape storage heavyweights at the LTO org says the medium's sales dropped significantly last year – by nearly 8 per cent – with 105,198PB of total tape capacity (compressed) shipped.
Tape shipments over the past few years have been increasing, and have been projected to grow considerably by 2025 by industry analyst IDC, which estimates data generated to the tune of a potential 175 zettabytes a year by then. With many vendors shifting to a hybrid cloud model, and all the data in the cloud needing to be backed up, much of this is cold storage – and currently this means the (relatively) cheaper option of tape.
However, in a statement accompanying the release of the report, the LTO consortium – comprising Program Technology Provider Companies HPE, IBM, and Quantum – conceded they'd been "optimistic for 2020," adding that "global shutdowns and other factors outside of our collective control led to a reduced performance."
Microsoft has released Windows Server 2022, an LTS edition that has five years mainstream support and 10 years extended support.
Windows Server 2022 is available only as an LTS release, since Microsoft has now abandoned the semi-annual channel in which releases were only supported for 18 months.
The operating system reports itself as version 21H2, which aligns with the next feature update for Windows 10, rather than with Windows 11 for which the build numbers begin 22000.
The British government has intervened in the US buyout of defence supplier Ultra Electronics, temporarily halting the acquisition and prohibiting any tech transfer overseas.
An order in Parliament was laid yesterday [PDF] that prohibits Ultra's buyer, Advent International, from receiving any of its intellectual property until further notice.
The business is a major supplier of high-end electronics to the Royal Navy and the other British armed forces. Among other items it supplies sonar systems for nuclear submarines, as well as aerospace components and subsystems.
The Document Foundation has released LibreOffice 7.2, including a native build for Apple Silicon though users are warned not to use it "for any critical purpose."
The new release is not a big one for features but is nevertheless notable for a couple of reasons.
First, there is now an official Apple Silicon build which can be found here, though the Foundation said that "because of the early stage of development on this specific platform, binaries are provided but should not be used for any critical purpose."
Microsoft and HPE were cock-a-hoop yesterday with the trumpeting of data bursts from HPE hardware aboard the International Space Station (ISS) to Microsoft's Azure, starting with the inevitable "hello world".
HPE's first spaceborne computer, based on an Apollo 40-class system, returned to Earth in 2019 after nearly two years aboard the ISS. The second went up earlier this year, replete with Red Hat 7.8 to keep things ticking over and software to handle any failures when components receive a zapping in the harsh environment aboard the ISS.
Oddly, Microsoft's bragging on the matter yesterday concerning data bursts pumped from HPE's hardware into Microsoft's cloud failed to mention that Linux was running the show. Windows for Space Stations, anyone?
Before the UK government launched its programme to extract patient data from GP systems in England and Wales – now twice-delayed – the National Data Guardian (NDG) warned the government could be "perceived as trying to introduce changes 'under the radar'".
The warning came from Dame Fiona Caldicott, architect of the current system for protecting patient confidentiality in England and Wales, and NDG until her untimely death in February 2021, before the programme described as the biggest data grab in NHS history was launched.
The NDG's annual report, published this week [PDF], said important lessons were learned from the past when planning and rolling out the new GP Data for Planning and Research programme (GPDPR). In 2016, the NHS scrapped an earlier system for sharing GP data, care.data, after spending £8m on the controversial programme.
Baidu, China's biggest search engine company, says it has started making an AI chip that will enable applications ranging from cloud services to autonomous cars.
The 7nm process Kunlun II, announced yesterday at the annual Baidu World conference, has a max power consumption of 120W, and is claimed to be two to three times faster than its predecessor.
Baidu will both use the chip in-house and sell it to others. A canned statement said Kunlun II can be applied in multiple scenarios – cloud, terminal, and edge – for a range of uses like biocomputing and intelligent transportation. Not to mention, of course, a main feature of the conference: autonomous driving.
A compiler bug in 64-bit Visual Basic for Applications (VBA) on Windows has existed unfixed for years, a user complained, and is blocking migration to 64-bit Office.
The problem – reported by a StackOverflow user – is in code that runs correctly in 32-bit VBA but not in the 64-bit version.
There are documented reasons why VBA code may need modifying to run in 64-bit mode, such as Declare statements that call the Windows API, but this is not one of those.
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Intel Alder Lake CPUs Will Feature 8+8 Core Design And A Massive 19% IPC Increase Over 11th Generation CPUs
19 August, 2021 - 08:10am
Intel’s Alder Lake will be built using the company’s new E and P cores, you can read the architectural deep dive over here, and represent a significant evolution in the company’s power efficiency targets. It will be built on the Intel 7 process and scale from 9 watts to 125 watts. DDR5 and PCIe gen5 will be supported (first to market) and feature new technologies like the Intel Thread Director.
Alder Lake will be fully scalable from Desktop (LGA1700) to ultra mobile. Interestingly however, while the platform has 8 P-cores and 8 E-cores, only the P-cores will support hyper threading making for a total of 24 threads available. The integrated GPU will have 96 EUs of Xe architecture (good but nothing to write home about) but the thing that impressed us the most was the fact that Intel is claiming a 19% IPC uplift over Rocketlake – which should handily beat AMD parts if true.
Rocketlake delivered 19% IPC uplift over Skylake as well but Skylake is almost a decade old architecture and Intel can repeat that trick again with Alder Lake, it should be able to beat AMD Ryzen parts core for core. That said, considering Ryzen parts have higher core counts on the mainstream side (16 performance cores), AMD should still retain the absolute performance crown until Intel roles out high core count parts with this architecture.
Alder Lake will feature up to 30 MB of non inclusive LL Cache and support DDR5-4800, LP5-5200 along with DDR4-3200 and LP4x-4266. It will also support two times the PCIe bandwidth thanks to its support of PCIe 5 and will be able to provide up to 16 lanes of PCIe Gen5 with up to 64 GB/s. The new design is fully modular and built like lego and should be completely scalable and flexible. The compute fabric interconnect has a bandwidth of 1000 GB/s while the IO fabric has a BW of 64 GB/s. The memory subsystem supports up to 204 GB/s but more importantly can scale memory frequency (and power) according to the need of the SoC.
Intel Alder Lake will be landing later this year in 2021 and should be able to win back the mobility performance and power efficiency crown from AMD. It might also be able to take the war to Apple’s M1 silicon although we expect AMD to retain the absolute performance count for now.
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19 August, 2021 - 08:00am
Quick refresher: Intel's Alder Lake architecture features a design reminiscent of ARM's big.LITTLE, with the larger cores used primarily for high-priority single-threaded work, while the smaller cores execute multi-threaded workloads and less-intensive background tasks. Intel uses a combination of 'big' Performance (P) Golden Cove cores and 'small' Efficiency (E) Atom Gracemont cores for the task. We'll dig deeper into the core architectures on the following pages.
The Alder Lake desktop PC chips will come with a maximum of eight performance cores and eight efficiency cores with a total of 24 threads (two threads per P-Core, one thread per E-Core). These chips will also top out with up to 30MB of L3 cache.
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19 August, 2021 - 08:00am
This week Intel held its annual Architecture Day event for select press and partners. As with previous iterations, the company disclosed details about its next generation architectures set to come to the market over the next twelve months. Intel has promised the release of its next-generation consumer and mobile processor family, Alder Lake, to come by the end of the year and today the company is sharing a good number of details about the holistic design of the chips as well as some good detail about the microarchitectures that form this hybrid design: Golden Cove and Gracemont. Here is our analysis of Intel’s disclosure.
For Alder Lake, the processor designs feature Performance cores based on a new Golden Cove microarchitecture, and Efficiency cores based on a new Gracemont architecture. We will cover both over the course of this article, however the idea is that the P-core is preferential for single threaded tasks that require low latency, and the E-core is better in power limited or multi-threaded scenarios. Each Alder Lake SoC will physically contain both, however Intel has not yet disclosed the end-user product configurations.
Each of the P-cores has the potential to offer multithreading, whereas the E-cores are one thread per core. This means there will be three physical designs based on Alder Lake:
Intel typically highlights UP4 mobile designs for very low power installs, down to 9 W, whereas UP3 can cover anything from 12 W to 35 W (or perhaps higher), but when asked about the power budgets for these processors, Intel stated that more detail will follow when product announcements are made. Intel did confirm that the highest client power, presumably on the desktop processor, will be 125 W.
Highlighted in our discussions is how modular Intel has made Alder Lake. From a range of base component options, the company mixed and matched what it felt were the best combination of parts for each market.
Here it shows that four E-cores takes up the same physical space as one P-core, but also that the desktop hardware will at most have 32 EUs (Execution Units) for Xe-LP graphics (same as the previous generation), while both of the mobile processors will offer 96 physical EUs that may be disabled down based on the specific line item in the product stack.
All three processors will feature Intel’s next generation Gaussian Neural Accelerator (GNA 3.0) for minor low power AI tasks, a display engine, and some level of PCIe, however the desktop processor will have more. Only the mobile processors will get an Image Processing Unit (IPU), and Thunderbolt 4 (TBT), and here the big UP3 mobile processor gets four ports of Thunderbolt whereas the smaller UP4 will only get two. The desktop processor will not have any native Thunderbolt connectivity.
We’ll cover a bit more detail about the core designs later in this article, but Intel did showcase some of the information on the desktop processor. It confirmed explicitly that there would be 16 total cores and 24 threads, with up to 30 MB of non-inclusive last level/L3 cache.
In contrast to previous iterations of Intel’s processors, the desktop processor will support all modern standards: DDR5 at 4800 MT/s, DDR4-3200, LPDDR5-5200, and LPDDR4X-4266. Alongside this the processor will enable dynamic voltage-frequency scaling (aka turbo) and offer enhanced overclocking support. What exactly that last element means we’re unclear of at this point.
Intel confirmed that there will not be separate core designs with different memory support – all desktop processors will have a memory controller that can do all four standards. What this means is that we may see motherboards with built-in LPDDR5 or LPDDR4X rather than memory slots if a vendor wants to use LP memory, mostly likely in integrated small form factor designs but I wouldn’t put it past someone like ASRock to offer a mini-ITX board with built in LPDDR5. It was not disclosed what memory architectures the mobile processors will support, although we do expect almost identical support.
On the PCIe side of things, Alder Lake’s desktop processor will be supporting 20 lanes of PCIe, and this is split between PCIe 4.0 and PCIe 5.0.
The desktop processor will have sixteen lanes of PCIe 5.0, which we expect to be split as x16 for graphics or as x8 for graphics and x4/x4 for storage. This will enable a full 64 GB/s bandwidth. Above and beyond this are another four PCIe 4.0 lanes for more storage. As PCIe 5.0 NVMe drives come to market, users may have to decide if they want the full PCIe 5.0 to the discrete graphics card or not
Intel also let it be known that the top chipset for Alder Lake on desktop now supports 12 lanes of PCIe 4.0 and 16 lanes of PCIe 3.0. This will allow for additional PCIe 4.0 devices to use the chipset, reducing the number of lanes needed for items like 10 gigabit Ethernet controllers or anything a bit spicier. If you ever thought your RGB controller could use more bandwidth, Intel is only happy to provide.
Intel did not disclose the bandwidth connectivity between the CPU and the chipset, though we believe this to be at least PCIe 4.0 x4 equivalent, if not higher.
The Alder Lake processor retains the dual-bandwidth ring we saw implemented in Tiger Lake, enabling 1000 GB/s of bandwidth. We learned from asking Intel in our Q&A that this ring is fully enabled regardless of whether the P-cores or E-cores are being used – Intel can disable one of the two rings when less bandwidth is needed, which would save power, however based on previous testing this single ring could end up drawing substantial power compared to the E-cores in low power operation. (This may be true in the mobile processors as well, which would have knock on effects for mobile battery life.)
The 64 GB/s of IO fabric is in line with the PCIe 5.0 x16 numbers we saw above, however the 204 GB/s of memory fabric bandwidth is a confusing number. Alder Lake features a 128-bit memory bus, which allows for 4x 32-bit DDR5 channels (DDR5 has two 32-bit channels per module, so 2 modules still), however in order to reach 204 GB/s in that configuration requires DDR5-12750; Intel has rated the processor only at DDR5-4800, less than half that, so it is unclear where this 204 GB/s number comes from. For perspective, Intel’s Ice Lake does 204.8 GB/s, and that’s a high-power server platform with 8 channels of DDR4-3200.
This final slide mentions TB4 and Wi-Fi 6E, however as with previous desktop processors, these are derived from controllers attached to the chipset, and not in the silicon itself. The mobile processors will have TBT integrated, but the desktop processor does not.
This slide also mentions Intel Thread Director, which we want to address on the next page before we get to the microarchitecture analysis.
19 August, 2021 - 08:00am
However, before we talk about new CPUs, we have to talk about the design of Intel’s new processors themselves, as the big changes to Intel’s core (no pun intended) architecture is what’s really paving the way for much of Intel’s performance and power efficiency gains.
And as you’d expect from a hot new CPU architecture, Alder Lake is also designed to better support new component standards including DDR5 RAM, PCIe Gen 5, Thunderbolt 4, Wi-Fi 6e, and more.
Furthermore, instead of focusing on the number of execution units, Alchemist’s architecture is based on what Intel is calling XE cores, which will be comprised of 16 vector engines and 16 matrix engines, with additional ray-tracing units that support both DirectX Raytracing and Vulkan Ray Tracing.
Unless they’re going to get to angstrom level manufacturing before everyone else (HAH!) they’re pretty much dead in the water. Especially now that they’re so desperate as to go to TSMC for their GPU manufacturing.